The present invention is directed to integrated circuits. More particularly, the invention provides a control system and method for over-current protection in the event of current sensing failures. Merely by way of example, the invention has been applied to a power converter. But it would be recognized that the invention has a much broader range of applicability.
Power converters are widely used for consumer electronics such as portable devices. The power converters can convert electric power from one form to another form. As an example, the electric power is transformed from alternate current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. Additionally, the power converters can convert the electric power from one voltage level to another voltage level.
The power converters include linear converters and switch-mode converters. The switch-mode converters often use pulse-width-modulated (PWM) or pulse-frequency-modulated mechanisms. For example, a PWM switch-mode converter is an offline flyback converter or a forward converter. These modulation mechanisms are usually implemented with a switch-mode controller including various protection components. These components can provide over-voltage protection, over-temperature protection, over-current protection (OCP), and over-power protection (OPP). These protections can often prevent the power converters and connected circuitries from suffering permanent damage.
FIG. 1 is a simplified conventional switch-mode power converter with over-current protection. A switch-mode power converter 100 includes an OCP comparator 110, a PWM controller component 120, a gate driver 130, a power switch 140, resistors 150, 152, 154, and 156, a primary winding 160, a secondary winding 162, an isolated feedback component 170, and a leading-edge-blanking component 192. The OCP comparator 110, the PWM controller component 120, the gate driver 130, and the leading-edge-blanking component 192 are parts of a chip 180 for PWM control, which includes terminals 182, 184, 186 and 188. Additionally, the PWM controller component 120 includes a PWM comparator 124 and a logic controller 126. As an example, the switch-mode power converter 100 is a conventional PWM flyback power converter.
As shown in FIG. 1, the PWM controller component 120 generates a PWM signal 122, which is received by the gate driver 130. In response, the gate driver 130 sends a gate signal 132 to the power switch 140 through the terminal 184. Accordingly, the power switch 140 adjusts the current 164 flowing through the primary winding 160. For example, if the power switch 140 is turned on, the power switch 140 is closed, allowing the current 164 to flow through the primary winding 160. In another example, if the power switch is turned off, the power switch 140 is open, thus not allowing the current 164 to flow through the primary winding 160.
The current 164 is sensed by the resistor 150 and converted into a current sensing signal 114 (e.g., Vcs) through the terminal 186 and the leading-edge-blanking component 192. The current sensing signal 114 is received by the OCP comparator 110 and compared with an over-current threshold signal 112 (e.g., Vth_oc). In response, the OCP comparator 110 sends an over-current control signal 116 to the PWM controller component 120. When the current of the primary winding is greater than a limiting level, the PWM controller component 120 turns off the power switch 140 and shuts down the switch-mode power converter 100, thus limiting the current 164 flowing through the primary winding 160 and protecting the switch-mode power converter 100.
More specifically, the output voltage of the secondary winding 162 is sensed by the isolated feedback component 170. For example, the isolated feedback component 170 includes an error amplifier and an opto-coupler. In response, the isolated feedback component 170 sends a feedback signal 123 to the PWM comparator 124 through the terminal 188. The PWM comparator 124 also receives the current sensing signal 114 and generates a PWM comparator output signal 125. The PWM comparator output signal 125 is received by the logic controller 126, which generates the PWM signal 122 based on at least information associated with the PWM comparator output signal 125.
FIG. 2 is a simplified diagram showing the conventional chip 180 for PWM control. The chip 180 includes the OCP comparator 110, the PWM comparator 124, the logic controller 126, the gate driver 130, the leading-edge-blanking component 192, a power-on-reset and under-voltage-lockout component 210, an internal power supply 220, a reference voltage and current generator 230, a clock and ramp signal generator 240, and a summation component 250. Additionally, the chip 180 also includes terminals 182, 184, 186, 188, 202 and 204.
As shown in FIG. 2, under normal operation, in each cycle, the current sensing signal 114 ramps up as the current 164 increase with time. The ramping-up slope of the current sensing signal 114 is
                    Slope        =                                            V              in                        ×                          R              s                                            L            p                                              (                  Equation          ⁢                                          ⁢          1                )            
where Vin represents an input voltage at a node 190, Rs represents the resistance value of the resistor 150, and Lp represents the inductance value of the primary winding 160.
The current sensing signal 114 is added to a ramp signal 244 by the summation component 250. The ramp signal 244 is generated by the clock and ramp signal generator 240, which also outputs a clock signal 242. The summation component 250 generates a summation signal 252, which is received by the PWM comparator 124. The PWM comparator 124 compares the summation signal 252 with the feedback signal 123 and outputs the PWM comparator output signal 125. The PWM comparator output signal 125 is received by the logic controller 126, which also receives a clock signal 242 and the over-current control signal 116.
For example, if the PWM comparator output signal 125 is at the logic low level, the summation signal 252 is larger than the feedback signal 123 in magnitude, and the power switch 140 is turned off. In another example, if the over-current control signal 116 is at the logic low level, the current sensing signal 114 is larger than the over-current threshold signal 112 (e.g., Vth_oc) in magnitude, and the power switch 140 is turned off.
FIG. 3 shows simplified conventional timing diagrams and waveforms for the switch-mode power converter 100 where the power switch 140 is turned off in response to the PWM comparator output signal 125. Curves 344, 342, 352, and 332 represent the signals 244, 242, 252, and 132 as functions of time respectively. When the summation signal 252 (corresponding to the curve 352) exceeds the feedback signal 123 (e.g., VFB) in magnitude, the gate signal 132 (corresponding to the curve 332) changes from the logic high level to the logic low level, causing the power switch 140 to be turned off.
FIG. 4 shows simplified conventional timing diagrams and waveforms for the switch-mode power converter 100 where the power switch 140 is turned off in response to the current sensing signal 114. Curves 444, 442, 414, and 432 represent the signals 244, 242, 114, and 132 as functions of time respectively. When the current sensing signal 114 (corresponding to the curve 414) exceeds the over-current threshold signal 112 (e.g., Vth_oc) in magnitude, the gate signal 232 (corresponding to the curve 432) changes from the logic high level to the logic low level, causing the power switch 140 to be turned off.
In more detail, the current 164 flowing through the primary winding 160 is limited to:
                              I          max                =                              V                          th              ⁢              _              ⁢              OC                                            R            s                                              (                  Equation          ⁢                                          ⁢          2                )            
where Imax is the predetermined maximum magnitude for the current 164. Additionally, Vth_oc represents the magnitude of the over-current threshold signal 112, and Rs represents the resistance value of the resistor 150. As discussed above, the current sensing signal 114 (corresponding to the curve 414) ramps up when the power switch 140 is turned on. If the current sensing signal 114 exceeds the predetermined Vth_oc, the over-current control signal 116 changes from the logic high level to the logic low level. As a result, the power switch 140 is turned off, thus limiting the current that flows through the primary winding 160 and preventing the switch-mode power converter 100 from being damaged by excessive current and voltage stress.
But the mechanism of over-current protection (OCP) as shown in FIGS. 1-4 usually cannot function properly if the sensing of the current 164 flowing through the primary winding 160 fails. For example, if the resistor 150 becomes shorted or if the terminal 186 becomes hard shorted with zero impedance or soft shorted with very low impedance to the ground, the current sensing signal 114 would become very small or nearly zero. The current sensing signal 114 cannot accurately represent the magnitude of the current 164, thus allowing excessively large magnitude of the current 164. The excessive current flowing through the primary winding 160 can cause damage to the switch-mode power converter 100 due to excessive current and voltage stress at switching or thermal run-away at operation. For example, the excessive current can cause the primary winding 160 to saturate. In another example, the rectifier components at the transformer secondary side may be subject to permanent damage and even fire due to excessively high voltage and current stress at operation.
Hence it is highly desirable to improve the techniques of over-current protection (OCP).